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A survey of circuit-level soft error mitigation methodologies

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Abstract

Soft errors created due to propagation of single event transients are a significant reliability challenge in modern VLSI. With advances in CMOS technology scaling, circuits become increasingly more sensitive to transient pulses caused by energetic particles. This work reviews some popular circuit level SET mitigation techniques developed for combinational logic and compares them with respect to area, power and delay overheads.

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Authors and Affiliations

  1. Electrical Engineering, Lamar University, P.O. 10029, Beaumont, TX, 77710, USA

    Selahattin Sayil

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  1. Selahattin Sayil
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Correspondence to Selahattin Sayil.

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Sayil, S. A survey of circuit-level soft error mitigation methodologies. Analog Integr Circ Sig Process 99, 63–70 (2019). https://doi.org/10.1007/s10470-018-1300-8

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  • DOI: https://doi.org/10.1007/s10470-018-1300-8

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