Partition Based Product Term Retiming for Reliable Low Power Logic Structure

Abstract

Filtering is the one of the core element in any of the low power VLSI signal processing architecture. Increasing filter tap length will cause on the hardware complexity and lead to more power dissipation. The digital circuit requires some specialized algorithm to achieve high speed or low power consumption thereby to increase the chip performance. In this research work a modified retiming algorithm is proposed to reduce power dissipation by placing the Flip flops at the resultant multiplication of the output nodes. The proposed architecture equations are simplified in terms of sum of product term and distribute the weight of product terms by applying retiming method. In the proposed architecture design the flip flops are placed to fan out of partition multiplication to minimize the switching activity factor. In this paper, to prove the performance of chip sum-of-product term retiming is applied, this can be implemented for any digital circuit to reduce total power. The proposed algorithms have been implemented in cadence EDA tool and the results are proved by using finite-impulse response (FIR) and infinite-impulse response (IIR) filters. Using Digital Signal Processing (DSP) application, proposed algorithm is synthesized to ensure that power saving is achieved compared to existing method. The method proves Energy per sample (EPS) as much better than node-splitting and node-merging technique. Experimental results shows power dissipation is minimized compared to other FIR architecture. Complete design task is modeled using Data Flow Graph (DFG) to achieve more precise result.