Abstract
The eight-bit stack processor architecture is proposed, which is designed for the FPGA implementation. The microprocessor with this architecture has small hardware costs, reduced software amount, and ability to add up to hundred new user instructions to its instruction set. The microprocessor architecture is adapted for programming the serial port communications and is able to perform the data stream parsing.
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References
Nurmi, J. (ed.): Processor Design. System-on-Chip Computing for ASICs and FPGAs. Springer, Netherlands (2007)
Chapman, K.: PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6). Xilinx, Inc., San Jose (2012)
Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays, 4th edn. Springer, Heidelberg (2014)
Al-Dujaili, A., Hiung, L.H., Tan, S.: ASH1: a stack-based input/output processor for USB operations. In: Proceedings of 2015 IEEE International Circuits and Systems Symposium (ICSyS), pp. 76–79. IEEE (2015)
Abouelella, F., Bruneel, K., Stroobandt, D.: Efficiently generating FPGA configurations through a stack machine. In: Proceedings of 2010 International Conference on Field Programmable Logic and Applications, pp. 35–39. IEEE (2010)
Hanna, D.M., Jones, B., Lorenz, L., Porthun, S.: An embedded Forth core with floating point and branch prediction. In: Proceedings of 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS’2013), pp. 1055–1058. IEEE (2013)
Hin, W.K., Chiu-Sing, C., Oliver: Littlel6 - small scale 16-bit controller architecture for FPGA systems flow control. In: Proceedings of TENCON 2015 - 2015 IEEE Region 10 Conference, pp. 1926–1929. IEEE (2015)
Jeemon, J.: Low power pipelined 8-bit RISC processor design and implementation on FPGA. In: Proceedings of 2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), pp. 476–481. IEEE (2015)
Daghooghi, T.: Design and development MIPS processor based on a high performance and low power architecture on FPGA. Int. J. Mod. Educ. Comput. Sci. (IJMECS) 5(5), 49–59 (2013). https://doi.org/10.5815/ijmecs.2013.05.06
Afzal, S., Hafeez, F., Akhter, M.O.: Single chip embedded system solution: efficient resource utilization by interfacing LCD through softcore processor in Xilinx FPGA. IJIEEB 7(6), 23–27 (2015). https://doi.org/10.5815/ijieeb.2015.06.04
Oyetoke, O.O.: A practical application of ARM Cortex-M3 processor core in embedded system engineering. Int. J. Intell. Syst. Appl. (IJISA) 9(7), 70–88 (2017). https://doi.org/10.5815/ijisa.2017.07.08
Rani, A., Grover, N.: Novel design of 32-bit asynchronous (RISC) microprocessor & its implementation on FPGA. Int. J. Inf. Eng. Electron. Bus. (IJIEEB) 10(1), 39–47 (2018). https://doi.org/10.5815/ijieeb.2018.01.06
Koopman, P.: Stack Computers: The New Wave. Ellis Horwood, Mountain View (1989)
Leong, P.H.W., Tsang, P.K., Lee, T.K.: A FPGA based forth microprocessor. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, Napa Valley (1998)
Paysan, B.: b16-small—Less is More. In: Proceedings EuroForth 2004, 9 July 2006
Bowman, J., Garage, W.: J1: a small Forth CPU Core for FPGAs. In: Proceedings EuroForth’2010, pp. 1–4, January 2010
Kelly, M., Spies, N.: Forth: A Text and Reference. Prentice Hall, Englewood Cliffs (1986)
Najafi, M., Sadoghi, M., Jacobsen, H.-A.: Configurable hardware-based streaming architecture using online programmable-block. In: ICDE 2015, Seoul, South Korea, 13–17 April, pp. 819–830 (2015)
Teubner, J., Woods, L., Nie, C.: XLynx—an FPGA-based XML filter for hybrid XQuery processing. ACM Trans. Database Syst. (TODS) 38(4), Article 23 (2013)
Maslennikov, O., Shevtshenko, J., Sergyienko, A.: Configurable microcontroller array. In: Proceedings Parallel Computing in Electrical Engineering, PARELEC’02, 25 September 2002, Warsaw, Poland, pp. 47–49. IEEE (2003)
Nios II Performance Benchmarks. DS-N28162004. Intel, pp. 1–7 (2018)
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Molchanov, O., Orlova, M., Sergiyenko, A. (2020). Software/Hardware Co-design of the Microprocessor for the Serial Port Communications. In: Hu, Z., Petoukhov, S., Dychka, I., He, M. (eds) Advances in Computer Science for Engineering and Education II. ICCSEEA 2019. Advances in Intelligent Systems and Computing, vol 938. Springer, Cham. https://doi.org/10.1007/978-3-030-16621-2_22
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DOI: https://doi.org/10.1007/978-3-030-16621-2_22
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