An Implementation of Bidirectional NOC Router for Reconfigurable Coarse Grained Architecture by Using Vedic Multiplier

Abstract

In Soc approaches Noc router performs an essential task. But in SoC chip, the routing operation performance is very complex. Since single Integrated Circuit carries millions of chips, to which each chip includes of millions of transistors. Therefore, NoC router is intended to facilitate effective routing operation in the SoC board. Crossbar Switches, arbiters, buffers, a routing logic, and Network Interconnects are incorporated in NoC router. Priority based Round Robin Arbiter (RRA) is used to design traditional unidirectional router. In unidirectional router area utilization has been consumed and it determines priority by the use of delay factor, which guarantee from different input channels. Moreover if any path failure appears, router cannot route the information across additional output channel. To conquer this difficulty, a new bidirectional NoC router with and without contention is projected, that provides small area and increased speed. Bidirectional router used to route the information from source channel to every destination channel. Therefore it overcomes dispute state and path malfunction troubles. If some path failure may occurs, directly it will take other path during the switch allocator. The projected architecture used to improve the speed of the interconnection link. Simulation result achieved by ModelSim6.3c and synthesis is approved out by Xilinx 12.4.