BJT and FET Models

Abstract

In Chaps. 2 and 3, the BJT and FET were introduced and their operation discussed. The need for biasing was established and various biasing schemes presented. Also, the operation of the BJT and FET as amplifiers each in three configurations was discussed. While the methods utilized gave reasonably good answers, more precise design requires the use of BJT and FET models or equivalent circuits. The models we adopt are the hybrid parameter or h-parameter model and the y-parameter model. These transistor parameters can in general be obtained from manufacturer’s data sheets. At the end of this chapter, the student will be able to:

Problems

• 1. Draw the h-parameter equivalent circuit for the common emitter amplifier shown in Fig. 4.71, and determine the voltage gain and input impedance. If a load resistor of 10 k is connected at the output, what will the new voltage gain?

  Fig. 4.71

  

  Circuit for Question 1

• 2. Draw the h-parameter equivalent circuit of a common emitter H-biased amplifier circuit, and derive the expression for the voltage gain, input impedance and output impedance.

• 3. Draw the equivalent circuit for the amplifier shown in Fig. 4.72 and determine the voltage gain. If a load resistor of 5 k is connected at the output, what will be the new voltage gain?

  Fig. 4.72

  

  Circuit for Question 3

• 4. For the circuit in question 3, determine the voltage gain if a 1 k resistor is connected in series with the input.

• 5. Draw the equivalent circuit for the partially decoupled common emitter amplifier shown in Fig. 4.73, and determine the voltage gain and the input impedance.

  Fig. 4.73

  

  Circuit for Question 5

• 6. Using the partially bypassed configuration in Fig. 4.73 of question 5, design a common emitter amplifier having a gain of 40, using a 2N3904 npn transistor and a 18 V power supply. Determine the input impedance.

• 7. Show that bootstrapping can increase the input impedance of a common emitter amplifier in the partially bypassed configuration. Use this technique to increase the input impedance of the design in question 6.

• 8. Using the configuration in Fig. 4.74, design a common emitter amplifier having a gain of 25, using an npn transistor and a 12 V power supply.

• 9. The common emitter amplifier in Fig. 4.75 is biased for maximum symmetrical swing. Determine the voltage gain for the circuit and the current gain of the transistor.

Fig. 4.74

Circuit for Question 8

Fig. 4.75

Circuit for Question 9

• 10. Using a supply voltage of 16 volts, design a collector-base feedback biased common emitter circuit with fixed gain of 12 using an emitter resistor and a transistor with h_fe = 150.

• 11. For the common collector amplifier shown in Fig. 4.76 determine the voltage gain, input impedance and output impedance.

  Fig. 4.76

  

  Circuit for Question 11

• 12. Improve the input impedance of the common collector amplifier in question 11 using bootstrapping.

• 13. For the common base amplifier shown in Fig. 4.77, determine the voltage gain, input impedance and output impedance.

  Fig. 4.77

  

  Circuit for Question 13

• 14. For the circuit shown in Fig. 4.78, draw the equivalent circuit. For R_L = 2 k, R_S = 1 k, R_G = 2 M and g_m = 8 mA/V, calculate the voltage gain and input impedance of the circuit.

  Fig. 4.78

  

  Circuit for Question 14

• 15. If the bypass capacitor is removed from the circuit, determine the new value of the voltage gain.

• 16. Draw the equivalent circuit of the common drain JFET amplifier in Fig. 4.79 and derive its voltage gain.

  Fig. 4.79

  

  Circuit for Question 16

• 17. For the circuit of Fig. 4.79, R₁ = 1.8 MΩ, R₂ = 1.5 MΩ, R_S = 2.2 kΩ and g_m = 4 mA/V_, find the voltage gain, input impedance and output impedance.

• 18. For the common gate amplifier shown in Fig. 4.80 if R_L = 3.2 k, R_S = 2.5 k and g_m = 5 mA/V, find the voltage gain and the input impedance.

  Fig. 4.80

  

  Circuit for Question 18

• 19. The common source depletion mode MOSFET in Fig. 4.81 has R_L = 10 k, R_G = 10 M and g_m = 9 mA/V. Draw the equivalent circuit and determine the voltage gain.

  Fig. 4.81

  

  Circuit for Question 19

• 20. Draw the equivalent circuit for the circuit in Fig. 4.81 with a bias resistor inserted in the source circuit.

• 21. Draw the equivalent circuit of the depletion MOSFET common drain amplifier.

• 22. Draw the equivalent circuit and derive the voltage gain and input impedance of the depletion MOSFET common gate amplifier.

• 23. Draw the equivalent circuit for the enhancement mode MOSFET common source amplifier shown in Fig. 4.82. Hence derive the expression for the voltage gain.

  Fig. 4.82

  

  Circuit for Question 23

• 24. Using the equation for the drain current, derive an expression for g_m.

• 25. Draw the equivalent circuit for the enhancement MOSFET common drain amplifier and derive the voltage gain.

• 26. Draw the equivalent circuit for the common gate enhancement MOSFET amplifier and determine the voltage gain and input impedance.

• 27. If the gate of an n-channel JFET is connected to the source, the gate-source voltage will be held at zero, and therefore if the drain-source voltage exceeds the pinch-off voltage, the drain current will be constant at IDSS. Explain how this arrangement can be used as a constant current source.

• 28. Is this arrangement possible with a p-channel JFET and if so how?

• 29. Discuss the use of an n-channel enhancement mode MOSFET in the source follower mode in place of an emitter follower BJT in enhancing a Zener diode regulator.

• 30. Is this arrangement possible with a p-channel enhancement mode MOSFET and if so how?