Abstract
Computing power has shown great significance in supporting various applications in daily life. With the continuous increase in demand for computing power in recent years, it is vital to provide a continuous increase of computing power through specialized architectures to meet the demands of modern complex algorithms and applications, given that the fabrication is reaching its physical limit. This research purposes a novel MAC unit based on a novel computing theory to reduce the latency of parallel multiplication-accumulation processes, such as matrix multiplication, convolution in deep learning and DFT. The novel MAC unit is implemented using Xilinx Vivado and Vitis IDE. With data collected from FPGA implementation and simulation in the design software, the result shows that a processing element that consists of 16/32 MAC units used 4−6 times more resources than the traditional implementation but has 9 times lower latency.
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This project is funded by a Royal Society Research Grant.
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Yan, F., Wang, X., Deng, T. (2023). Bit-Level Operation-Based MAC Unit for Vector Multiplications. In: Arai, K. (eds) Intelligent Computing. SAI 2023. Lecture Notes in Networks and Systems, vol 711. Springer, Cham. https://doi.org/10.1007/978-3-031-37717-4_1
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DOI: https://doi.org/10.1007/978-3-031-37717-4_1
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