A Novel Architecture of High-Speed and Area-Efficient Wallace Tree Multiplier Using Square Root Carry Select Adder with Mirror Adder

Abstract

Multipliers are important blocks in designing various digital and high-performance systems, such as processors, signal processing circuits, communication systems. To design high-performance systems, the multiplier used in them should be designed efficiently. Among various multiplier designs, Wallace tree multiplier is fastest in operation. The adder is the main circuit in any multiplier design whose speed of operation affects the performance of multiplier. Among different adder topologies, Square root Carry Select Adder (SQRT CSLA) is good in performance which can be used in the Wallace tree multiplier design as adder block to achieve high performance. In this proposed multiplier design, SQRT CSLA block is modified by replacing Ripple Carry Adder blocks with mirror adder and Binary to Excess-1 Converter (BEC) in order to achieve high performance and less area. Wallace tree multipliers of 4-bit and 8-bit are designed in Verilog. The proposed multiplier is functionally verified using Xilinx ISIM simulator and later synthesized using XST synthesizer in Xilinx ISE design suite. The proposed design of multiplier is compared with at present Wallace tree multiplier designs in terms of number of LUTs and delay (ns).