Abstract
In this paper, different 32-bit carry-skip adders, i.e., Fixed Stage Size-Conventional carry-skip adder (FSS-Conv CSKA), Variable Stage Size-Conventional carry-skip adder (VSS-Conv CSKA), Fixed Stage Size-Concatenation and Incrementation carry-skip adder (FSS-CI CSKA) and Variable Stage Size-Concatenation and Incrementation carry-skip adder (VSS-CI CSKA) are designed and compared in terms of power, energy, critical path delay, power-delay product, and energy-delay product using 45 nm static CMOS technology for different range of supply voltages, i.e., 0.7v, 0.9v, 1.1v. The results that are obtained using tanner EDA simulations reveal that the Concatenation and Incrementation carry-skip adder with fixed and variable stage size has 51 and 49% improvement in the critical path delay and energy, compared with those of fixed stage size-conventional carry-skip adder and Variable Stage Size-Conventional carry-skip adder.
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Sanjana, B., Ragini, K. (2019). Design of a Novel High-Speed- and Energy-Efficient 32-Bit Carry-Skip Adder. In: Saini, H., Singh, R., Kumar, G., Rather, G., Santhi, K. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 65. Springer, Singapore. https://doi.org/10.1007/978-981-13-3765-9_35
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DOI: https://doi.org/10.1007/978-981-13-3765-9_35
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