Analysis and characterization of leakage reduction methodologies for stacking, body biasing and DLS in 65 nm CMOS technology Dima KilaniBaker MohammadMohammed Ismail OriginalPaper 10 August 2019 Pages: 1 - 8
A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates Ankur KumarR. K. Nagaria OriginalPaper 15 June 2019 Pages: 9 - 25
On the design and analysis of a compact array with 1T1R RRAM memory element Khaoula MbarekFaten Ouaja RzigaKamel Besbes OriginalPaper 28 June 2019 Pages: 27 - 37
A wide-range all-digital phase inversion DLL for high-speed DRAMs Jongsun Kim OriginalPaper 05 September 2019 Pages: 39 - 51
Power and delay optimization of domino Schmitt trigger configurations with enhanced hysteresis voltage S. Balaji RamakrishnaS. MadhusudhanH. D. Teerthaprasad OriginalPaper 16 September 2019 Pages: 53 - 61
Efficient design of QCA based hybrid multiplier using clock zone based crossover K. PandiammalD. Meganathan OriginalPaper 16 December 2019 Pages: 63 - 77
A CMOS temperature sensor based on duty-cycle modulation with calibration An-Qiang GuoQuan SunDonghai Qiao OriginalPaper 03 May 2019 Pages: 79 - 89
A highly linear and high-accurate CMOS image sensor Masood Teymouri OriginalPaper 25 October 2019 Pages: 91 - 96
CMOS time-mode smart temperature sensor using programmable temperature compensation devices and \(\Delta \Sigma\) time-to-digital converter R. S. S. M. R. KrishnaAshis Kumar MalRajat Mahapatra OriginalPaper 09 October 2019 Pages: 97 - 109
An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications Sanjay VidhyadharanRamakant YadavSurya Shankar Dan OriginalPaper 22 November 2019 Pages: 111 - 123
A fully integrated digitally controllable grounded inductor simulator with a large inductance range for damping of ultrasonic transducers Jan LedvinaPavel Horský OriginalPaper 25 January 2019 Pages: 125 - 130
An energy-efficient multi-level RF-interconnect for global network-on-chip communication Majid JalalifarGyung-Su Byun OriginalPaper 04 May 2019 Pages: 131 - 143
An effective hybrid approach for PAPR reduction in MIMO-OFDM M. VijayalakshmiK. Ramalinga Reddy OriginalPaper 26 June 2019 Pages: 145 - 153
Layout optimization of planar inductors for high-efficiency integrated power converters Ahmed H. ShaltoutStefano Gregori OriginalPaper 08 July 2019 Pages: 155 - 167
VLSI architecture for analog radix-4 DFT front-end in QAM–OFDM receiver Anirban GangulyAyan Banerjee OriginalPaper 17 October 2019 Pages: 169 - 179
Analog 8-point DFT processor with low-power consumption and high-speed for interference mitigation in GPS receivers A. NobahariM. SafariP. Amiri OriginalPaper 15 October 2019 Pages: 181 - 203
A 2.4 GHz quadrature LC-VCO with combination of tunable pulse coupling and parallel coupling to optimize phase noise Na XiTianchun YeFujiang Lin OriginalPaper 26 November 2019 Pages: 205 - 212
CMOS integrated delay chain for X-Ku band applications Mohammad Hossein GhazizadehFateme DaryabariAli Medi OriginalPaper 20 December 2019 Pages: 213 - 224
A test point selection approach for DC analog circuits with large number of predefined faults Masoumeh KhanlariMehdi Ehsanian OriginalPaper 02 November 2019 Pages: 225 - 235
An efficient feature extraction approach based on manifold learning for analogue circuits fault diagnosis Zhijie YuanYigang HeZhen Cheng OriginalPaper 14 December 2018 Pages: 237 - 252
Low-power asymmetric switching scheme with segmented capacitive architecture for SAR ADCs Peiyi YueYanbo ZhangZhangming Zhu Mixed Signal Letter 25 November 2019 Pages: 253 - 264
2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs Peng WangJie Sun Mixed Signal Letter 16 December 2019 Pages: 265 - 271
