1. Guest Editorial

   • Imed Ben Dhaou
   • Hannu Tenhunen
   • Keshab K. Parhi

   OriginalPaper Pages: 191 - 192

2. Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

   • Xiao-Dong Yang
   • Chung-Kuan Cheng
   • Robert Carragher

   OriginalPaper Pages: 193 - 208

3. The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

   • Kevin T. Tang
   • Eby G. Friedman

   OriginalPaper Pages: 209 - 224

4. Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows

   • M. Graziano
   • G. Masera
   • M. Zamboni

   OriginalPaper Pages: 225 - 248

5. Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

   • Kevin T. Tang
   • Eby G. Friedman

   OriginalPaper Pages: 249 - 259