1. Interconnect Macromodelling and Approximation of Matrix Exponent

   • V.G. Kurbatov
   • M.N. Oreshina

   OriginalPaper Pages: 5 - 19

2. Common-Mode Response Overlapping vs. Shaping in Rail-to-Rail Op-Amp Input Stages

   • J. Francisco Duque-Carrillo
   • Juan M. Carrillo
   • José L. Ausín

   OriginalPaper Pages: 21 - 29

3. A Wide Bandwidth Isolation Amplifier Design Using Current Conveyors

   • An Sang Hou

   OriginalPaper Pages: 31 - 38

4. A Rank Encoder: Adaptive Analog to Digital Conversion Exploiting Time Domain Spike Signal Processing

   • Philipp Häfliger
   • Elin Jørgensen Aasebø

   OriginalPaper Pages: 39 - 51

5. A Square-Root Domain Differentiator Circuit

   • Spiridon Vlassis
   • Costas Psychalinos

   OriginalPaper Pages: 53 - 59

6. A Balanced Capacitive Threshold-Logic Gate

   • Javier López-García
   • José Fernández-Ramos
   • Alfonso Gago-Bohórquez

   OriginalPaper Pages: 61 - 69

7. Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

   • Antonio J. López-Martín
   • Alfonso Carlosena
   • Jaime Ramirez-Angulo

   OriginalPaper Pages: 71 - 74

8. A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor

   • Mohamed A. Youssef
   • Ahmed M. Soliman

   OriginalPaper Pages: 75 - 82

9. Novel Canonic Current Mode DDCC Based SRCO Synthesized Using a Genetic Algorithm

   • Varun Aggarwal

   OriginalPaper Pages: 83 - 85

10. SITO High Output Impedance Transadmittance Filter Using FTFNs

    • N.A. Shah
    • S.Z. Iqbal
    • B. Parveen

    OriginalPaper Pages: 87 - 89

11. New Wide Band Low Power CMOS Current Conveyors

    • Wessam S. Hassanein
    • Inas A. Awad
    • Ahmed M. Soliman

    OriginalPaper Pages: 91 - 97

12. A Four Quadrant Analog Multiplier Employing Single CDBA

    • Ali Ümit Keskin

    OriginalPaper Pages: 99 - 101

13. A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits

    • Fei Yuan

    OriginalPaper Pages: 103 - 108