1. A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

   • Kaustubha Mendhurwar
   • Harsh Sundani
   • Vijay Devabhaktuni

   OriginalPaper 10 May 2011 Pages: 265 - 281

   

2. Fast-settling CMOS Op-Amp with improved DC-gain

   • Ali Dadashi
   • Shamin Sadrafshari
   • Abdollah Khoei

   OriginalPaper 19 June 2011 Pages: 283 - 292

   

3. Symbolic noise modeling, analysis and optimization of a CMOS input buffer

   • Santosh Kumar Patnaik
   • Swapna Banerjee

   OriginalPaper 21 July 2011 Pages: 293 - 302

   

4. A high-speed rail-to-rail output buffer with push–pull dual-path and dynamic-bias for LCD driver ICs

   • Chien-Hung Tsai
   • Jia-Hui Wang

   OriginalPaper 12 August 2011 Pages: 303 - 310

   

5. Spatially oversampled TDC with digital resolution enhancement

   • Kameswaran Vengattaramane
   • Jonathan Borremans
   • Jan Craninckx

   OriginalPaper 16 June 2011 Pages: 311 - 322

   

6. An ultra low die area 8-b ADC and its generic calibration logic

   • Nikos Petrellis
   • Michael Birbas

   OriginalPaper 14 July 2011 Pages: 323 - 335

   

7. A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator

   • HeungJun Jeon
   • Yong-Bin Kim

   OriginalPaper 17 July 2011 Pages: 337 - 346

   

8. A digital processor for full calibration of pipelined ADCs

   • Mohammad Fardad
   • Javad Frounchi
   • Ghader Karimian

   OriginalPaper 23 July 2011 Pages: 347 - 356

   

9. Nonlinearity analysis of folded Multi-LSB decided resistor string digital to analog converter

   • Chun-Chieh Chen
   • Nan-Ku Lu
   • Yi-Zhi Zeng

   OriginalPaper 21 July 2011 Pages: 357 - 367

   

10. A mathematical steady-state design model for fully-integrated boost and buck DC–DC converters

    • Mike Wens
    • Michiel Steyaert

    OriginalPaper 19 April 2011 Pages: 369 - 375

    

11. Power aware channel width tapering of serially connected MOSFETs

    • Sudhanshu Choudhary
    • S. Qureshi

    OriginalPaper 07 July 2011 Pages: 377 - 383

    

12. A new true RMS-to-DC converter using up-down translinear loop in CMOS technology

    • E. Farshidi
    • H. Asiaban

    OriginalPaper 13 July 2011 Pages: 385 - 390

    

13. Robust feedforward compensation scheme with AC booster for high frequency low voltage buck DC–DC converters

    • Chunming Zhang
    • Zhibiao Shao

    OriginalPaper 22 July 2011 Pages: 391 - 404

    

14. Fast-response single-inductor dual-output hysteresis-current-controlled DC–DC buck converter

    • Jiann-Jong Chen
    • Bo-Han Hwang
    • Cheng-Chieh Yu

    OriginalPaper 23 July 2011 Pages: 405 - 415

    

15. Analysis and modeling of an improved dual-array D/A network for SAR A/D converter

    • Xing Yuan Tong
    • Zhang Ming Zhu
    • Yin Tang Yang

    Mixed Signal Letter 17 July 2011 Pages: 417 - 420

    

16. Power efficient high-speed DAC for wideband communication applications

    • Jaejin Jung
    • Sangho Shin
    • Sung-Mo Kang

    Mixed Signal Letter 04 August 2011 Pages: 421 - 428

    

17. Mismatch reduction technique for transistors with minimum channel length

    • Marvin Onabajo
    • Jose Silva-Martinez

    Mixed Signal Letter 06 August 2011 Pages: 429 - 435

    

18. A second-harmonic LC-quadrature voltage controlled oscillator with direct connection of MOSFETs’ substrate

    • Mohammad Jafar Hemmati
    • Sasan Naseh

    Mixed Signal Letter 12 August 2011 Pages: 437 - 442

    

19. On ‘Discussion on Barkhausen and Nyquist stability criteria’

    • Herminio Martínez-García
    • Antoni Grau-Saldes
    • Juan Gámiz-Caro

    Mixed Signal Letter 14 August 2011 Pages: 443 - 449

    

20. A novel concept for phase noise improvement in monolithic differential LC-VCOs

    • Hamid Reza Sadr-M. N.
    • Massoud Dousti

    Mixed Signal Letter 18 August 2011 Pages: 451 - 454

    

21. Electronically tunable CMOS class-AB output stage

    • S. Vlassis

    Mixed Signal Letter 19 August 2011 Pages: 455 - 459