1. A MOS translinear cell-based configurable block for current-mode analog signal processing

   • Mohammad Moradinezhad Maryan
   • Seyed Javad Azhari

   OriginalPaper 06 April 2017 Pages: 1 - 13

   

2. Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

   • Rajeev Kumar Ranjan
   • Kaushik Mazumdar
   • Satish Chandra

   OriginalPaper 12 April 2017 Pages: 15 - 27

   

3. A high linearity current-controlled CMOS relaxation oscillator with frequency self-calibration technique

   • Yangyang Lu
   • Jing Zhu
   • Jian Chen

   OriginalPaper 19 April 2017 Pages: 29 - 37

   

4. A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

   • Nicolas Dehaese
   • Inès Ben Amor
   • Sylvain Bourdel

   OriginalPaper 05 May 2017 Pages: 39 - 53

   

5. A novel pulse swallow based frequency divider circuit for a phase-locked loops

   • Manas Kumar Hati
   • Tarun K. Bhattacharyya

   OriginalPaper 22 April 2017 Pages: 55 - 69

   

6. Highly stable analog front-end design for NFC smart card

   • Trio Adiono
   • Amy Hamidah Salman
   • Suksmandhira Harimurti

   OriginalPaper 28 April 2017 Pages: 71 - 79

   

7. Dual-time resolution time-based transceiver for low-power serial interfaces

   • Mostafa Rashdan

   OriginalPaper 20 April 2017 Pages: 81 - 89

   

8. Asymmetrically CPW-fed ladder-shaped fractal antenna for UWB applications

   • Sarthak Singhal
   • Amit Kumar Singh

   OriginalPaper 19 April 2017 Pages: 91 - 101

   

9. RF transceiver and transmission line behavioral modeling in VHDL-AMS for wired RFNoC

   • Lounis Zerioul
   • Myriam Ariaudo
   • Emmanuelle Bourdel

   OriginalPaper 25 April 2017 Pages: 103 - 114

   

10. A programmable 40 Gb/s SST driver with high-frequency signal-boost capability in 28 nm CMOS

    • Khaldoon Abugharbieh
    • Karam Gharbieh

    OriginalPaper 05 April 2017 Pages: 115 - 129

    

11. FVF LDO regulator with dual dynamic-load composite gain stage

    • Chengpeng Li
    • Pak Kwong Chan

    OriginalPaper 17 April 2017 Pages: 131 - 140

    

12. An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

    • Sandeep Kumar
    • Jinwong Choi
    • Hanjung Song

    OriginalPaper 25 April 2017 Pages: 141 - 149

    

13. A low power sub-BGR with multi-curvature self-compensation

    • Junchao Mu
    • Lianxi Liu

    Mixed Signal Letter 05 April 2017 Pages: 151 - 158

    

14. Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

    • Antaryami Panigrahi
    • Abhipsa Parhi

    Mixed Signal Letter 06 April 2017 Pages: 159 - 165

    

15. New CMOS realization of high performance Voltage Differencing Inverting Buffered Amplifier and its filter application

    • Shweta Kumari
    • Maneesha Gupta

    Mixed Signal Letter 12 April 2017 Pages: 167 - 178